Tetsu TANAKA, Ph.D.


Graduate School of Biomedical Engineering, Tohoku University

Tetsu Tanaka received the B.S. and M.S. degrees in electronics engineering and the Ph.D. degree in machine intelligence and systems engineering from Tohoku University, Sendai, Japan, in 1987, 1990, and 2003, respectively. The title of doctoral dissertation is “A Study of High-Performance and Ultra-Small MOSFET Technology.” In 1990, he joined Fujitsu Laboratories, Ltd., where he was engaged in the research and development of the highly-scaled Metal-Oxide-Semiconductor (MOS) devices including Silicon-on-Insulator (SOI) devices. From 1994 to 1995, he was a Visiting Fellow with University of California, Berkeley, where he studied a device characterization and modeling with Professor Chenming Hu. Prof. Tanaka invented a p+-n+ double-gate SOI MOSFETs in 1993, and developed 1T-DRAM with GIDL current writing method in 2003. In 2005, he moved to the Tohoku University as an Associate Professor, and became a Professor of Graduate School of Biomedical Engineering, Tohoku University in 2008. After joining Tohoku University, he is working on the research and development of integrated biomedical micro/nano-devices and systems using semiconductor process/device/circuit technologies and neural engineering. His current research topics include:

1. Intelligent Si neural probe and brain-machine interface

2. Fully-implantable retinal prosthesis system

3. Three-dimensional integration technology and analog/digital LSI design

4. Bio/nano technology and novel Bio-FET sensor.

He has published more than 150 technical papers and given more than 30 invited talks. He was jointly awarded the 2010 Outstanding Paper Award of the 60th Electronic Components and Technology Conference (ECTC) in 2010, and IEEE Solid-State Circuits Society (SSCS) Kansai Chapter Academic Research Award in 2013. He has or had served as a technical committee member or an editor of various international conferences and journals, such as IEEE Electron Devices Society Japan Chapter Treasurer (2006~2007), IEEE Electron Devices Society Japan Chapter Secretary (2008~2009), International Interconnect Technology Conference (IITC, 2008~), International Conference on Solid State Devices and Materials (SSDM, 2008~), Symposium on VLSI Technology (2009~), International Electron Devices Meeting (IEDM, 2011~2012), and Japanese Journal of Applied Physics (JJAP, 2009~2011). Moreover, he had also served as a WG member of International Technology Roadmap for Semiconductors (ITRS, 2006~2016), which played an important role to make clear semiconductor roadmap to anticipate the evolution of the market and to plan and control the technological needs of integrated circuit (IC) production.